1. Field of Invention
The present invention is related to testing semiconductor integrated circuit chip and in particular the testing of CMOS driver circuits.
2. Description of Related Art
The evolution of integrated circuit chips has resulted in chips with a higher density of circuits, more I/O pads and a larger variety of functions. Testing these chips has required testers with many expensive pin electronics to allow the testing of a large variety of chips where input pin on one chip is an output pin on another chip. Further complicating the requirements of an output pin is that the driver may be relatively low or high power. Also the driver may operate at a relatively low or high voltage. The driver may be single ended or biased between two voltages. Thus the cost of the pin electronics increases as a tester accommodates the variety of possible configurations. Further as the complexity of the tester increases, the amount of testing devices in parallel becomes limited.
High pin count SOC (system on chip) devices and in particular those with a high number of output drivers can benefit from a test technique utilizing a subset of I/O pins or pads. This would reduce the number of connections to be made, lowering the cost of probe cards, or sockets, ease the control of the contacting process. A lower pin count test might leave out DC performance of unconnected pins/pads, which could be acceptable where a second final test after packaging is performed, but is not acceptable for single test insertion devices that are delivered as tested.
U.S. Pat. No. 6,725,171 (Baur et al.) is directed to bi-directional I/O that takes advantage of the of the ability to use a complimentary device to serve as a load for the transistor under test and cause a voltage drop that is accessed by the input circuit and converted to a digital signal. US 2007/0208526 is directed to reconfiguring a load transistor in to a current mirror and to provide the mirror current available for comparison or direct measurement. U.S. Pat. No. 6,593,765 (Ishida et al.) is directed to a testing apparatus in which test patterns are applied to an integrated circuit chip to activate a circuit path, wherein measurements of chip power supply transient current is used to detect a fault in the activated circuit path. U.S. Pat. No. 6,847,203 (Conti et al.) is directed to an integrated circuit chip apparatus that has contact pads to make contact with signal input/output pins of the chip being tested. An intermediate banking box is used that reduces the number of tester channels connected to the integrated circuit chip.
FIG. 1 displays another method to determine drive capability of an output driver of an integrated circuit chip without the use of instrumentation in the pin electronics of a tester. A capacitor C on a load board is connect to a chip pad connected to a bidirectional I/O circuit where data loaded into the driver is enabled EN and the time constant of the output driver 10 driving the capacitor C is measured by the receiver circuit 11.
Many of the tricks to reduce the need of expensive pin electronics in a tester revolve around bidirectional I/O where the input circuit is used to measure the response of the output circuit to a test procedure. When the bidirectional capability does not exist at a chip output pad, as is the case for high voltage drivers, other techniques need to be used.